A semiconductor memory device including a memory cell array in which memory cells capable of setting plural physical quantity levels are arranged, and simultaneously selected two memory cells make up a pair cell to be a unit of date storage is known (for example, refer to Patent Document 1). In the semiconductor memory device, one of “N” (N is an integer of 3 or more) pieces of physical quantity levels is set at each memory cell, and in each pair cell, the physical quantity levels of the two memory cells making up the pair cell are different, and each pair cell stores an M-value data (where M>N) represented by M=2n (where “n” is an integer of 2 or more) which is defined by a combination state in which differences between the physical quantity levels are different.
Besides, a memory of a multi-level cell using plural magneto-tunnel junctions is known (for example, refer to Non-Patent Document 1).
[Patent Document 1] Japanese Laid-open Patent Publication No. 2006-260711
[Non-Patent Document 1] T. Ishigaki et al., “A Multi-Level-Cell Spin-Transfer Torque Memory with Series-Stacked Magnetotunnel Junctions”, 2010 Symposium on VLSI Technology Digest of Technical Papers, 2010, PP. 47-48
In the memory of the multi-level cell using the plural magneto-tunnel junctions, determination of the multi-level becomes difficult when variation of resistance values of the multi-level cell becomes large.